I'm a beginner using verilog. I am trying to make a simple parallel to serial converter (8 bits parallel down to 1 bit serial). I have 2 textbooks but I think it is way too complicated for me to understand. Right now when I try to simulate my simple Parallel-to-Serial module the input of 8-bits parallel appear but only 1 of the 8 serial bit appear.
SIPO module sipomod(clk,clear, si, po); input clk, si,clear; output [3:0] po; reg [3:0] tmp; reg [3:0] po; always @(posedge clk) begin if (clear) tmp.
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 module piso1 (sout,sin,clk ); output sout; input [ 3: 0 ]sin; input clk; wire [ 3: 0 ]q; inv u1 (p,sl ); and1 u2 (n,sin [ 1 ],p ); and1 u3 (r,sl,q [ 0 ] ); or1 u4 (s,n,r ); and1 u5 (t,sin [ 2 ],p ); and1 u6 (u,sl,q [ 1 ] ); or1 u7 (v,u,t ); and1 u8 (w,sin [ 3 ],p ); and1 u9 (y,sl,q [ 2 ] ); or1 u10 (z,w,y ); dff1 u11 (q [ 0 ],sin [ 0 ],clk ); dff1 u12 (q [ 1 ],s,clk ); dff1 u13 (q [ 2 ],v,clk ); dff1 u14 (q [ 3 ],z,clk ); assign sout = q [ 3 ]; endmodule. 